W24257S-70LL T/R

W24257 32K × 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24257 is a slow speed, low power CMOS static RAM organized as 32768 × 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • • • • Low power consumption: − Active: 325 mW (max.) − Standby: 75 µW (max.) (LL-version) 150 µW (max.) (L-version) Access time: 70 nS (max.) Single +5V power supply Fully static operation • • • • PIN CONFIGURATION All inputs and outputs directly TTL compatible Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged in 28-pin 330 mil SOP, standard type one TSOP (8 mm x 13.4 mm ) BLOCK DIAGRAM VDD VSS A14 1 28 V DD A12 2 27 WE A0 . . DECODER A14 CORE ARRAY A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O8 SYMBOL I/O1 11 18 I/O7 A0−A14 I/O2 12 17 I/O6 I/O1−I/O8 I/O3 13 16 I/O5 CS Chip Select Input VSS 14 15 I/O4 WE Write Enable Input OE VDD VSS Output Enable Input CS OE CONTROL DATA I/O WE I/O1 . . I/O8 PIN DESCRIPTION -1- DESCRIPTION Address Inputs Data Inputs/Outputs Power Supply Ground Publication Release Date: May 2000 Revision A14 W24257 TRUTH TABLE MODE VDD CURRENT I/O1−I/O8 CS H OE X WE X L L H L H H Not Selected Output Disable Read High Z High Z Data Out ISB, ISB1 IDD IDD L X L Write Data In IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER VSS Supply Voltage to Potential Input/Output to VSS Potential Allowable Power Dissipation RATING UNIT -0.5 to +7.0 -0.5 to VDD +0.5 1.0 V V W -65 to +150 °C 0 to +70 °C Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Low Voltage Input High Voltage Input Leakage Current VIL VIH ILI - -0.5 +2.2 -2 - +0.8 VDD +0.5 +2 V V µA Output Leakage Current ILO -2 - +2 µA Output Low Voltage VOL VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or WE = VIL (max.) IOL = +4.0 mA - - 0.4 V Output High Voltage Operating Power Supply Current VOH IDD IOH = -1.0 mA 2.4 - - 65 V mA Standby Power Supply Current ISB CS = VIH (min.) Cycle = min., Duty = 100% - - 3 mA ISB1 CS ≥ VDD -0.2V LL - - 15 µA L - - 30 µA VIN = VSS to VDD CS = VIL (min.), I/O = 0 mA Cycle = min., Duty = 100% Note: Typical characteristics are at VDD = 5V, TA = 25° C. -2- W24257 CAPACITANCE (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.6V to 2.4V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load CL = 100 pF, IOH/IOL = -1 mA/4 mA AC Test Loads and Waveform R1 1000 ohm 5V R1 1000 ohm 5V OUTPUT OUTPUT 5 pF 100 pF Including Jig and Scope R2 660 ohm Including Jig and Scope R2 660 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ , TOW) 3.0V 90% 10% 0V 90% 10% 5 nS 5 nS -3- Publication Release Date: May 2000 Revision A14 W24257 AC Characteristics, continued (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) Read Cycle PARAMETER SYMBOL W24257-70 UNIT MIN. MAX. 70 - Read Cycle Time TRC Address Access Time TAA - 70 nS Chip Select Access Time TACS - 70 nS Output Enable to Output Valid TAOE - 35 nS Chip Selection to Output in Low Z TCLZ* 10 - nS Output Enable to Output in Low Z TOLZ* 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 nS Output Disable to Output in High Z TOHZ* - 30 nS Output Hold from Address Change TOH 10 - nS nS ∗ These parameters are sampled but not 100% tested Write Cycle PARAMETER SYMBOL W24257-70 UNIT MIN. MAX. Write Cycle Time TWC 70 - nS Chip Selection to End of Write TCW 60 - nS Address Valid to End of Write TAW 60 - nS Address Setup Time TAS 0 - nS Write Pulse Width TWP 45 - nS TWR 0 - nS Data Valid to End of Write TDW 30 - nS Data Hold from End of Write TDH 0 - nS Write to Output in High Z TWHZ* - 30 nS Output Disable to Output in High Z TOHZ* - 30 nS Output Active from End of Write TOW 0 - nS Write Recovery Time CS, WE ∗ These parameters are sampled but not 100% tested -4- W24257 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH DOUT Read Cycle 2 (Chip Select Controlled) CS TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address T AA OE T OH T AOE T OLZ CS T ACS D OUT T CHZ T OHZ TCLZ -5- Publication Release Date: May 2000 Revision A14 W24257 Timing Waveforms, continued Write Cycle 1 TWC Address T WR OE TCW CS T AW WE T WP TAS TOHZ (1, 4) D OUT T DW TDH D IN Write Cycle 2 ( OE = VIL Fixed) T WC Address TWR TCW CS TAW WE TOH T WP TAS TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24257 DATA RETENTION CHARACTERISTICS (TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS VDD for Data Retention VDR CS ≥ VDD -0.2V Data Retention Current IDDDR CS ≥ VDD -0.2V VDD = 3V Chip Deselect to Data Retention Time TCDR See data retention Operation Recovery Time waveform TR MIN. TYP. MAX. UNIT 2.0 - - V LL - - 15 µA L - - 30 µA 0 - - nS TRC* - - nS T RC* = Read Cycle Time DATA RETENTION WAVEFORM DATA RETENTION MODE VDD 4.5V TCDR 4.5V TR CS1 > = VDD -0.2V VIH CS VDR > = 2V VIH ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (µA) W24257S-70LL 70 65 15 330 mil SOP W24257S-70L 70 65 30 330 mil SOP W24257Q-70LL 70 65 15 Standard type one TSOP W24257Q-70L 70 65 30 Standard type one TSOP PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: May 2000 Revision A14 W24257 BONDING PAD DIAGRAM 6 A4 5 4 A5 A6 3 2 1 30 29 28 27 26 25 24 A7 A12 A14 VDD VDD WEB A13 A8 A9 A11 AC5394 23 7 A3 OEB Y X 8 22 A2 A10 9 10 A1 A0 I/O0 I/O1 I/O2 VSS 11 12 13 14 15 16 17 18 19 20 21 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CSB PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X -232.25 -351.70 -471.15 -590.60 -710.05 -829.50 -992.79 -992.79 -857.86 -738.41 -594.84 -451.06 -310.67 -171.78 24.45 151.80 298.07 443.28 588.20 732.84 871.11 992.75 992.75 810.09 690.64 571.19 451.74 332.29 120.25 -93.23 Y 1445.22 1445.22 1445.22 1445.22 1445.22 1445.22 1362.24 -1306.11 -1452.79 -1452.79 -1414.13 -1414.13 -1414.13 -1405.28 -1405.28 -1414.13 -1414.13 -1414.13 -1414.13 -1414.13 -1452.79 -1312.15 1373.67 1445.22 1445.22 1445.22 1445.22 1445.22 1444.65 1444.65 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. -8- Publication Release Date: May 2000 Revision A14 W24257 PACKAGE DIMENSIONS 28-pin SO Wide Body Symbol 28 A A1 A2 b c D E e HE L LE S y θ 15 e1 E HE L Detail F 14 1 b Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 2.85 0.112 0.004 0.10 0.093 0.098 0.103 2.36 2.49 0.014 0.016 0.020 0.36 0.41 2.62 0.008 0.010 0.014 0.20 0.713 0.733 0.326 0.331 0.336 8.28 8.41 8.53 0.044 0.050 0.056 1.12 1.27 1.42 0.51 0.25 0.36 18.11 18.62 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.036 0.044 0.71 0.91 1.12 0.059 0.067 0.075 1.50 1.70 1.91 0.047 1.19 0.10 0.004 10 0 10 0 Notes: 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. e1 D c A2 A S e y LE A1 See Detail F Seating Plane 28-pin Standard Type One TSOP HD Dimension In Inches Dimension In mm Symbol Min. D c A A1 A2 b c D E HD e L L1 Y θ 1 e E b A2 A θ A1 L Nom. Max. Min. Nom. 0.002 Max. 1.20 0.047 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.008 0.011 0.17 0.20 0.27 0.004 0.006 0.008 0.10 0.15 0.21 11.90 1.05 0.461 0.465 0.469 11.70 11.80 0.311 0.315 0.319 7.90 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 0.028 0.50 0.022 0.020 0.024 0.55 0.010 0.000 0 3 0.60 0.70 0.25 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters Y L1 -9- Publication Release Date: May 2000 Revision A14 W24257 VERSION HISTORY VERSION DATE PAGE A12 Nov. 1999 1, 2, 7 DESCRIPTION Change the IDD, ISB, ISB1 4, 7 A13 Apr. 2000 7 A14 May 2000 1, 7, 8 Remove the W24257-10 spc. Typo correction in Standby Current Max.: mA->µA Delete 28-pin DIP Package 8 Headquarters Add in Bonding Pad Diagram Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. - 10 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798